1. Field of the Invention
The present invention relates in general to data processing systems, and in particular, to data processing systems and methods for mitigation latencies in data processing systems including.
2. Description of the Related Art
Modern signal processing systems, such as those found, for example, in commercial and consumer audio and multimedia products, are moving, with improvements in Very Large Scale Integration (VLSI) fabrication processes, to xe2x80x9csystem on a chipxe2x80x9d (SoC) implementations. Such implementations may include one or more processors which may perform signal processing and control functions, on-chip memory, and signal amplification whereby an amplified signal may be delivered directly to the user""s listening device, a speaker or a headphone set, for example.
As the sources of digital audio, video and multimedia data have become more sophisticated, the tasks required of the play back systems have correspondingly become more complex. For example, the source stream may be delivered in a compressed format in accordance with one or more standardized compression formats, such as those promulgated by the Motion Picture Experts Group (MPEG). Additionally, the compressed digital audio data may be embedded in a multiplexed bitstream that includes additional data, for example, conditional access information which may be used to limit the access to the underlying content to users who have subscribed thereto. Consequently, the digital signal processing demands placed upon the SoC may be significant. Thus, such an SoC may incorporate a DSP engine to perform the computationally intensive signal processing required to extract and recover the uncompressed digital data. Instructions and data for the DSP engine may be stored in memory which may be on chip, off chip, or a combination of both. Typically, the speed of the DSP exceeds that of the memory devices, and in modem DSP systems the memory latency can be long enough to stall the DSP engine while the memory transaction (read/write) completes. Buffers inserted between the memory system and the DSP may be used to reduce latency penalties associated with memory reads by speculatively prefetching and storing instructions or data. However, systems using such buffer mechanisms have, heretofore remained vulnerable to memory latencies with respect to writes to memory.
Consequently, there is a need in the art for systems and methods to shield a DSP(or similar high-performance processor) from memory latencies. In particular, there is a need for such systems and methods adapted for both read and write transactions.
According to the principles of the present invention, a buffer apparatus is disclosed that includes a read buffer unit configured for storing at least one data value read from a memory device, and a write buffer unit configured for storing at least one data value for writing to the memory device. The read buffer unit is operable for updating with the at least one data value for writing to the memory device in response to a write to the write buffer unit.
The inventive concept addresses a problem modem signal processing systems, such as those found, for example, in commercial and consumer audio and multimedia products, particularly, with improvements in Very Large Scale Integration (VLSI) fabrication processes, xe2x80x9csystem on a chipxe2x80x9d (SoC) implementations. As the sources of digital audio, video and multimedia data have become more sophisticated, the tasks required of the play back systems have correspondingly become more complex. Consequently, the digital signal processing demands placed upon the SoC may be significant, and such an SoC may incorporate a DSP engine to perform the computationally intensive signal processing required to extract and recover the uncompressed digital data. Instructions and data for the DSP engine may be stored in memory which may be on chip, off chip, or a combination of both. Typically, the speed of the DSP exceeds that of the memory devices, and in modern DSP systems the memory latency can be long enough to stall the DSP engine while the memory transaction (read/write) completes. The read and write buffers units of the present invention may mitigate against memory latencies while maintaining coherency between the data therein.